1. Field of the Invention
The present invention relates to a memory testing apparatus for testing various types of semiconductor memories, and more particularly, to such memory testing apparatus suitable for testing a memory in the form of semiconductor integrated circuit (hereinafter, referred to as IC), which adopts double data rate system and operates in burst mode.
2. Description of the Related Art
In sequentially transferred data, a set of plural data treated as one unit by a specified rule among them is called "burst" in this technical field, and a memory storing therein such a set of plural data (burst) as one unit is called "memory operates in bust mode" or "burst operation type memory" in this technical field. Also, a memory arranged such that it outputs two data in one clock period or cycle is called "double data rate type memory" or "memory adopting double data rate system" in this technical field. In this specification, the above definitions are also incorporated therein.
A semiconductor integrated circuit memory (an IC memory) which adopts double data rate system and operates in burst mode internally generates two address signals in one clock period or cycle. For this reason, in the case that a memory testing apparatus tests an IC memory of such type and supplies failure cell information of the IC memory obtained from the test result to a failure analysis memory of the testing apparatus to store the information therein, like the internal operation of the IC memory, it is necessary that the memory testing apparatus apply two address signals to the failure analysis memory in one test period or cycle corresponding to one clock period in the IC memory.
FIG. 4 shows a general construction of the conventional memory testing apparatus for testing IC memories. As shown in the drawing, the memory testing apparatus 1 comprises a timing generator 7, a pattern generator 2, a logical comparator 4, a failure analysis memory (failure memory) 5, and a system controller 6. The timing generator 7 supplies a reference clock to the pattern generator 2 and the system controller 6 respectively. Further, the reference clock supplied to the system controller 6 is given as a test period signal TI for defining one test period or cycle in the memory testing apparatus 1.
The pattern generator 2 generates, in response to the reference clock supplied thereto from the timing generator 7, an address signal, a test signal of a predetermined pattern (a test pattern signal) S1 and a control signal which are to be supplied to an IC memory to be tested or under test 3 (commonly called MUT). Also, the pattern generator 2 generates an expected value signal of a predetermined pattern (an expected value pattern signal) S2 to be supplied to the logical comparator 4, an address signal AD to be supplied to the failure analysis memory 5, and the like. In addition, the address signal, the test pattern signal S1 and the control signal to be supplied to the IC memory under test 3 (hereinafter, referred to as memory under test or MUT) 3 are inputted to a waveform shaping device (not shown) where they are shaped to waveforms required to test the memory under test 3, and thereafter the shaped waveforms are applied to the memory under test 3.
The memory under test 3 is controlled in its writing operation in which a test pattern signals S1 is written thereinto or its reading operation in which the written data signal is read out thereof by a control signal applied to the memory under test 3 through the waveform shaping device, and under the control of this control signal, a test pattern signal S1 supplied from the waveform shaping device is written into the memory under test 3 or the written test pattern signal is read out thereof. The test pattern signals written into the memory under test 3 are read out later which are, in turn, supplied to the logical comparator 4 where the read out signals S3 are sequentially compared with expected value pattern signals S2 supplied from the pattern generator 2 one by one, thereby to detect whether there is an anti-coincidence or a discord between the read out signal S3 and the expected value pattern signal S2. By these comparison results, a decision is rendered that the memory under test 3 is a failure (defective or non-conforming) memory or a pass (conforming or good) memory.
When there is a discord between both signals, a failure signal FD of usually logic "1" (high level) indicating that this memory cell is not defective or good is outputted from the logical comparator 4 to the failure analysis memory 5 in which a failure data corresponding to this failure signal FD is stored at an address of the failure analysis memory 5 specified by an address signal AD supplied thereto from the pattern generator 2. In general, when the read out signal S3 coincides with the expected value pattern signal S2, the logical comparator 4 generates a pass signal of usually logic "0" (low level) indicating that this memory cell is defective or failure, but a data corresponding to this pass signal is not stored in the failure analysis memory 5.
Usually, the address signal supplied to the MUT 3 on reading the stored test pattern signal out of the MUT 3 is also supplied to the failure analysis memory 5, and hence the failure data is stored in the failure analysis memory 5 at the same address as that of the failure memory cell of the MUT 3.
In such a way, failure data each representing a position of a failure memory cell of the memory under test 3, which have occurred during a sequence of tests, are stored in the failure analysis memory 5. After completion of the tests, a failure analysis of the memory under test 3 is performed with reference to the failure data stored in the failure analysis memory 5. For example, in case such failure data are utilized for relieving the failure memory cells, a failure map is created based on the read out failure data to determine whether the detected failure positions (failure memory cells) can be relieved by relieving means previously provided on the memory under test 3.
Incidentally, in the case that the memory under test 3 operates in burst mode, an address signal which is added to the test pattern signal S1 and is applied to the memory under test 3 from the pattern generator 2 is only one burst leading address signal (also called the first address signal) which indicates an address of the leading or head data (the first data) in the burst, and burst address signals indicating addresses of the second and subsequent data in the burst are automatically produced internally of the memory under test 3 in synchronism with the rising edge and the falling edge of an internal clock in the memory under test 3. For example, if the burst leading address signal is fetched in at the rising edge of an internal clock in the memory 3, the subsequent burst address signals are automatically produced internally of the memory 3 in synchronism with the falling edge of that internal clock, the rising edge and the falling edge of a subsequent internal clock, . . . .
In order to give to or store in the failure analysis memory 5 the failure information at all of the addresses of the memory under test 3 which is operating in burst mode, it is required that the pattern generator 2 produces not only the first address signal but also the subsequent burst address signals automatically produced in the inside of the memory under test 3 and these burst address signals including the first address signal are supplied to the failure analysis memory 5.
The pattern generator 2 outputs the above-mentioned various kinds of signals in accordance with a pattern generating program previously stored in a memory of the system controller 6 when the program is supplied to the pattern generator 2 as a pattern generating instruction from the system controller 6. For this end, the pattern generating program previously stored in the memory of the system controller 6 is created such that the pattern generator 2 generates, in addition to address signals to be supplied to the memory under test 3, address signals to be supplied to the failure analysis memory 5 in accordance with this pattern generating program.
By way of example, it is assumed that the memory under test 3 operates in burst mode and adopts double data rate system, and that the burst length is over four addresses (the burst size is of four data), and the burst address signals produced internally of the memory under test 3 is in sequence of ADR0, ADR1, ADR2, ADR3 from the first to the last. A timing chart showing waveforms and address signals produced in main elements of the memory testing apparatus 1 in such case is illustrated in FIG. 5.
FIG. 5A shows a test period signal TI supplied to the system controller 6 from the timing generator 7, FIG. 5B shows the first address signal (the burst leading address signal) supplied to the memory under test 3 from the pattern generator 2, FIG. 5C shows an internal clock produced internally of the memory under test 3, and FIG. 5D shows the burst address signals produced internally of the memory under test 3.
When the memory under test 3 takes the burst leading address (the first address) signal ADR0 as shown in FIG. 5B therein at the rising edge of a first internal clock CL1 shown in FIG. 5C, it produces by itself the first address signal ADR0 as well as the subsequent burst address signals ADR1, ADR2, ADR3 as shown in FIG. 5D in synchronism with the falling edge of the first internal clock CL1, the rising edge and the falling edge of a second internal clock CL2 respectively. As is clear from FIG. 5D, the memory under test 3 produces two burst address signals in one internal clock period Tt such as ADR0 and ADR1 in the first internal clock period, and ADR2 and ADR3 in the second internal clock period. In this example, the rise timing and the fall timing of each internal clock locates at the center of each of the burst address signals ADR0-ADR3 produced internally of the memory under test 3. The burst address signals including the first address signal ADR0 supplied to the failure analysis memory 5 from the pattern generator 2 is shown in FIG. 5E.
As discussed above, one clock period in the memory under test 3 corresponds to one test period in the memory testing apparatus 1. For this reason, in the case of storing in the failure analysis memory 5 the failure cell information of the memory under test 3 adopting double data rate system, it is desired to apply two address signals to the failure analysis memory 5 in one test period.
However, as described above, the conventional memory testing apparatus 1 is constructed such that only one address signal can be generated in one test period Tt from the pattern generator 2, and hence the measurement or test for IC memories is divided into two parts as show in FIG. 5, and the measurement for IC memories is performed two times one part by one part. That is, in the first function test, the pattern generator 2 generates for each test period Tt only the burst address signals ADR0 and ADR2 as shown in FIG. 5E corresponding to the burst address signals ADR0 and ADR2 shown in FIG. 5D in the first half of each test period Tt among the burst address signals ADR0-ADR3 produced internally of the memory under test 3, thereby to supply the burst address signals ADR0 and ADR2 to the failure analysis memory 5. Thereafter, in the second function test, the pattern generator 2 generates for each test period Tt only the burst address signals ADR1 and ADR3 as shown in FIG. 5E corresponding to the burst address signals ADR1 and ADR3 shown in FIG. 5D in the latter or second half of each test period Tt among the burst address signals ADR0-ADR3 produced internally of the memory under test 3, thereby to supply the burst address signals ADR1 and ADR3 to the failure analysis memory 5. In such way, by two function tests, all of the failure cell information of the memory under test 3 are stored in the failure analysis memory 5.
As mentioned above, a memory under test which operates in burst mode and adopts double data rate system internally generates two addresses in one clock period. Therefore, in the case of storing the failure cell information of the memory under test in the failure analysis memory 5 of the memory testing apparatus 1, it is desired to apply two address signals to the failure analysis memory 5 in one test period as in the internal operation of the memory under test. However, the conventional memory testing apparatus 1 cannot generate two address signals in one test period.
Consequently, two pattern generating programs are separately prepared, one for executing generation of address signals in the first half of each test period and the other for executing generation of address signals in the latter half of each test period, and the function test for IC memories is divided into two parts, one part being performed by use of the one pattern generating program, and the other part being performed by use of the other pattern generating program. By such two function tests, all of the failure cell information of the memory under test are stored in the failure analysis memory 5.
Accordingly, there is a drawback that in the conventional memory testing apparatus the test time period becomes twice as many, resulting in reduction of the throughput. Moreover, such programming is complicated, which imposes heavy burden or load on programmers.